The invention relates to a receiver for frequency modulated signals comprising a channel selection and intermediate frequency circuit; a phase-locked loop (PLL) frequency demodulator; and a return lead to the channel selection circuit, constituting a frequency-locked loop for the local tuning oscillator of the selection and IF circuit.
Such a receiver is known, for example from British patent application GB-A-2079552, to which U.S. Pat. No. 4,399,560 corresponds. The receiver described in this document uses three distinct phase detectors for determining a correction signal, with two detectors contributing to the formation of this correction signal and the third detector controlling the supply of this signal to the channel selection circuit. The control inputs of the local tuning oscillator and the phase-locked-loop demodulator oscillator are switched between a start-up mode and a locked-on mode. In the start-up mode the first phase detector controls the demodulator oscillator, and the tuning oscillator is controlled from a resistor network. In the locked on mode, the first detector controls the tuning oscillator, and another resistive network control the modulator oscillator's average frequency.